description the AS2916 is a dual, full featured, pulse width modulation controller. the second controller is intended to run the auxiliary supply. both controllers share common oscillator and power up logic. based on an improved as3842, the AS2916 provides additional features that reduce component count and improve specifications in a wide range of power supply designs. the added functionality also includes bulk voltage sensing, overvoltage input and soft start. the pwm function is controlled by the current sense comparator for normal current mode control and a second comparator for voltage mode soft start. a buffered ramp signal is available for slope compensation without loading the oscillator. the output stage is a high current totem pole output that sees only 140 ns delay from the pwm comparators. the AS2916 requires less than 25 m a of startup current. the undervoltage lockout (uvlo) thresholds are nominally 13.5 v for turn on and 7.5 v for turn off. the oscillator discharge current is trimmed to provide guaranteed duty cycle clamping. the AS2916 has a second low frequency oscillator, which frequency modulates the operating frequency of the pwm by 25 %, thus reducing emi emissions.. pinout AS2916 16l pdip 16l soic gnd pgnd outb vcc outa snsa snsb reg AS2916 bok cmpa cmpb ss on wbl osc ramp AS2916 primary side pwm controller s i link silicon link, inc
pin function description pin number function description 1 outb this is the gate drive output for the main fet. the totem pole output has equivalent of an extra 10 w resistor to limit the fet turn on speed and a pull down reisistor to ensure the fet gate is never open. no external circuitry except for the fet is expected on this pin. the largest fet expected to be driven is irfbc40. if a larger power fet is used, a buffer might be required. 2 vcc positive supply for the ic. absolute maximum rating is 20 v. the running voltage shall be provided by the auxiliary convertor. 3 reg output of 5 v series regulator. 4 snsb this is the main convertor current sense pin. an external rc filter from the main power fet and slope compensation resistor from the ramp pin is all the expected external circuitry. 5 cmpb this is the main output control pin. an opto isolated control signal from the secondary side error amplifier is buffered and connected to the invert pin of the main output current mode comparator. a pull-up current of 1 ma is provided so the only external circuitry expected is a common emitter opto- isolator. 6 ss this pin provides a 6 m a current source to linearly charge an external capacitor. this pin is compared to the ramp pin in the soft start comparator, terminating output pulses when ramp goes above the ss voltage. while this pin is held low, the main output is inhibited. 7 ramp this pin is a level-shifted and buffered oscillator waveform, used to provide slope compensation for the main and auxiliary converters. the pin also serves as the non-inverting input of the soft-start comparator. 8 osc oscillator frequency and maximum duty cycle are set by connecting a resistor (r t ) to vreg and a capacitor (c t ) to ground. 9 wbl provides an fm modulation of the oscillator, approximately 25 % deviation frequency, at a modulation rate set by an external cap at wbl. shorting to gnd eliminates modulation. 10 on this pin is used to remotely turn the main convertor on/off either for normal user application or for protection. 11 bok bulk ok. this is a brownout protection feature. the pin monitors the bulk voltage through a resistor divider. when bok exceeds 2.5 v a 50 m a current is sourced from the pin for hysteresis. when the pin drops below 2.5 v the hysteresis is turned off and ss is pulled low, inhibiting the main output. the auxiliary output is not tied to bok and will run as long as there is sufficient bias voltage. 12 cmpa this is the auxiliary convertor error amplifier compensation pin or if secondary controller is desired, the auxiliary control input pin. a simple capacitor to ground is the only circuitry expected. note: there is no external connection for voltage feedback. voltage sensing is provided internally in such way that vcc is not loaded until it reaches predefined threshold. if secondary control is required, it can be forced into the cmpa pin. 13 snsa this is the auxiliary convertor current sense pin. an external rc filter from the auxiliary power fet and slope compensation resistor from the ramp pin is all the expected external circuitry. silicon link, inc
pin number function description 14 outa this is the gate drive output for the auxiliary fet. the totem pole output has equivalent of an extra 33 w resistor to limit the fet turn on speed and a pull down reisistor to ensure the fet gate is never open. no external circuitry except for the fet is expected on this pin. the largest fet expected to be driven is irf820. if a larger power fet is used, a buffer might be required. 15 gnd signal ground. 1 6 pgnd power ground. absolute maximum ratings parameter symbol rating unit reference current i ref 200 ma output current i out 1a supply voltage v cc 20 v output voltage v out 20 v continuous power p d 500 mw junction temperature t j 150 c storage temperature t stg -60 to 150 c lead temperature (soldering, 10 seconds) t l 300 c electrical characteristics parameter symbol test condition min typ max unit 5 v regulator electrical characteristics are guaranteed over the full junction temperature range (0-105 c). ambient temperature must be derated based upon power dissipation and package thermal characteristics. the conditions are: vcc = 15 v, bok = 3 v, on = 3 v, r t = 680 w , c t = 10 nf, and c wbl =2.2nf, unless otherwise stated. to override uvlo, vcc should be raised above uvlo high prior to test. output voltage v reg i reg = 1 ma, t j = 25 c 4.9 5.00 5.1 v line regulation psrr 12 v cc 18 v 5 15 mv load regulation 1 i reg 20ma 5 15 mv temperature stability tc reg 0.2 0.4 mv/ c total output variation line, load,temperature 4.85 5.15 v long-term stability over 1,000 hrs at 25 c525mv output noise voltage v noise 10 f 100khz, t j = 25 c50 m v maximum source current i max v reg = 4.8 v 30 120 180 ma silicon link, inc
oscillator wobble oscillator auxiliary pwm comparator input (cmpa) initial frequency f osc t j = 25 c, v wbl = 0 v 117 132 143 khz voltage stability 8.5 vcc 18 v 0.2 1 % temperature stability tc f t min t j t max 5% amplitude v osc v osc peak-to-peak 1.55 v upper trip point v h v wbl = 0 v 2.8 v lower trip point v l v wbl = 0 v 1.25 v discharge current i dsc v osc = 3 v 7.5 8.7 9.5 ma duty cycle limit r t = 680 w , c t = 10 nf, t j = 25 46 50 54 % over-temperature shutdown t ot 140 c wobble rate f wbl 2.2 nf wbl to gnd 3.4 4.5 6.0 khz osc frequency deviation dev change in main oscillator frequency +30 +40 +50 khz amplitude v wbl v wbl peak-to-peak 1.8 v upper trip point v h 2.7 v lower trip point v l 0.9 v charge current i chrg v wbl = 0.7 v -25 -36 -50 m a discharge current i dsc v wbl = 4.8 v 25 36 50 m a regulation voltage vcc reg 13.4 14.5 15.7 v transconductance g m 1ms output sink current i cmpalow vcc = 16v, v cmpa = 1.1v 2 6 ma output source current i cmpahigh vcc = 12v, v cmpa = 5v -0.5 -1.1 ma output swing high v cmpahigh vcc = 12v, i cmpa = 0.5ma 5.4 5.7 v output swing low v cmpalow vcc = 16v, i cmpa = 2ma 0.2 1.1 v silicon link, inc
auxiliary current sense comparator (snsa) main pwm comparator input (cmpb) main current sense comparator (snsb) soft start comparator transfer gain a vsnsa -0.2 v snsa 0.8 v 3.00 v/v cmpa level shift v ls v snsa = 0v 1.5 v current sense threshold v snsa v cmpa = 5v 0.95 1.05 1.15 v input bias current i bias -1 -10 m a propagation delay to output t pd 80 150 ns comp source current i cmpb v cmpb = 2.5v -1 -1.4 ma comp source impedance z cmpb 10 15 20 k w comp swing high v cmpbhigh 5.4 5.6 v transfer gain a vsnsb -0.2 v snsb 0.8 v 3.00 v/v cmpb level shift v ls v snsb = 0v 1.5 v current sense threshold v snsb v cmpb = 5v 0.95 1.05 1.15 v input bias current i bias -1 -10 m a propagation delay to output t pd 80 150 ns ss charge current i charge ss v ss v ramp -4 -6 -10 m a ss discharge current i dsc ss v ss =1 v , v on < 1.5 v 2 10 ma ss lower clamp v ss low 0.05 0.2 v propagation delay to output t pb 50 100 ns ramp high level v ramph t j = 25 c 2.0 2.15 2.3 v ramp low level v rampl t j = 25 c 0.45 0.6 0.75 v ramp levels t c note: ramp waveform is same as osc waveform, but level shifted down one diode drop -2 mv/ c ramp sink current i rampl t j = 25 c 0.1 0.2 ma ramp source current i ramph t j = 25 c -2 -10 ma silicon link, inc
main output auxiliary output under-voltage lockout output low level v outbl i sink = 10 ma 0.1 0.4 v output low level v outbl i sink = 150 ma 1.5 2.2 v output high level v outbh i source = 10 ma, vcc= 15v 1 2 1 3 v output high level v outbh i source = 150 ma, vcc = 15v 1 0 10.7 v on resistance high 10 w rise time t r c l = 1.3nf, 10%-90% 50 150 ns fall time t f c l = 1.3nf, 90%-10% 50 150 ns output impedance to gnd in uvlo state z out vcc = 6 v 2 0 k w output low level v outbl i sink = 10 ma 0.1 0.4 v output low level v outbl i sink = 150 ma 1.5 2.2 v output high level v outbh i source = 10 ma, vcc= 15v, v cmpa = 5v 12 13 v output high level v outbh i source = 110 ma, vcc =15v, v cmpa = 5v 78 v on resistance high 33 w rise time t r c l = 350 pf, 10%-90% 70 150 ns fall time t f c l = 350 pf, 90%-10% 50 150 ns output impedance to gnd in uvlo state z out vcc = 6 v 2 0 k w start-up threshold vcc (on) 12.4 13.5 14.7 v stop threshold vcc (off) 7 7.5 8 v start-up current i cc 0.1 25 m a operating supply current i cc vcc = 15 v 18 25 ma silicon link, inc
housekeeping bok uv threshold v bok uv t j = 25 c 2.50 2.537 2.575 v bok uv hysteresis current i hyst bok v bok = 2.6 v 42 50 58 m a bok input bias current i bok v bok = 2.4 v -0.1 -1 m a on threshold v on 2.35 2.5 2.65 v on hysteresis d v on -0.7 -0.9 -1.1 v on bias current i bias on v on = 2.3 v -0.5 -10 m a silicon link, inc
AS2916 primary pwm on vcc uvlo 5v reg. reg cmpb 2r r snsb 1v osc rt/ct ss vreg 6 m a x1 ramp cm pwm outb gnd ss pwm 50 m a bok 2v5 vreg vcc snsa cm pwm outa gnd vcc cmpa r 1v osc wbl 2r x1 gm vcc s r q ? aux_on aux_on 2v5 (blank) (blank) 5v_enable (pwm) (pwm) (bulk_ok) (run) silicon link, inc
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